Systems architecture - OCRThe fetch-decode-execute cycle
Von Neumann architecture provides the basis for the majority of the computers we use today. The fetch-decode-execute cycle describes how a processor functions.
The fetch-decode-execute cycle is followed by a processor to process an instruction. The cycle consists of several stages.
The memoryThe part of a computer that stores data. address held in the program counter is copied into the MAR.
The address in the program counter is then incremented (increased) by one. The program counter now holds the address of the next instruction to be fetched.
The processor sends a signal along the address busThis is a one-way bus which requests data from an address in memory. to the memory address held in the MAR.
The instruction/data held in that memory address is sent along the data bus to the MDR.
The instruction/data held in the MDR is copied into the CIR.
The instruction/data held in the CIR is decoded and then executed. Results of processing are stored in the ACC.
The cycle then returns to step one.
Depending on the type of instruction, additional steps may be taken:
If the instruction is to transfer data held in the ACC back to primary memory, the intended memory address is copied into the MAR. The data to be transferred is copied into the MDR and then transferred to the specified address using the address bus and data bus.
The executed instruction may require the program to jump to a different place in the program. In this case, the memory address of the new next instruction to be fetched is copied into the program counter. The process then restarts at step one.
