Systems architecture - AQAThe fetch-execute cycle

The fetch-execute cycle (also known as fetch-decode-execute cycle) is followed by a processor to process an instruction. The cycle consists of several stages.

1. The memory address held in the program counter is copied into the MAR.
2. The address in the program counter is then incremented - increased - by one. The program counter now holds the address of the next instruction to be fetched.
3. The processor sends a signal along the address bus to the memory address held in the MAR.
4. The instruction/data held in that memory address is sent along the data bus to the MBR/MDR.
5. The instruction/data held in the MBR/MDR is copied into the CIR.
6. The instruction/data held in the CIR is decoded and then executed. Results of processing are stored in the ACC.
7. The cycle then returns to step one.